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ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 1 of 67 ibis5-a-1300 1.3m pixel dual shutter mode cmos image sensor datasheet
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 2 of 67 table of content 1 introduction....................................................................................................... 4 2 specifications..................................................................................................... 6 2.1 p ixel characteristics ......................................................................................... 6 2.2 e lectro - optical specifications ......................................................................... 6 2.2.1 overview .......................................................................................................... 6 2.2.2 spectral response curve ................................................................................... 7 2.2.3 photo-voltaic response curve........................................................................... 8 2.3 f eatures and general specifications .............................................................. 8 2.4 e lectrical specifications .................................................................................. 9 2.4.1 absolute maximum ratings............................................................................... 9 2.4.2 recommended operating conditions ................................................................ 9 2.4.3 dc electrical characteristics ......................................................................... 10 3 architecture and operation ................................................................. 11 3.1 f loor plan .......................................................................................................... 11 3.2 p ixel ..................................................................................................................... 12 3.2.1 architecture.................................................................................................... 12 3.2.2 color filter array............................................................................................ 12 3.3 f rame rate .......................................................................................................... 13 3.3.1 rolling shutter................................................................................................ 13 3.3.2 snapshot shutter............................................................................................. 14 3.3.3 region-of-interest (roi) read out................................................................. 14 3.4 i mage core operation ....................................................................................... 15 3.4.1 image core operation and signalling ............................................................. 15 3.4.2 image core supply considerations.................................................................. 16 3.4.3 image core biasing signals ............................................................................ 17 3.4.4 pins involved in the image core circuitry ...................................................... 18 3.5 x- addressing ...................................................................................................... 20 3.6 y- addressing ...................................................................................................... 22 3.7 o utput amplifier ................................................................................................ 23 3.7.1 architecture and settings ............................................................................... 23 3.7.2 output amplifier gain control ........................................................................ 24 3.7.3 setting of the dac reference voltages ........................................................... 24 3.7.4 pins involved in the output amplifier circuitry .............................................. 25 3.8 a nalog to digital converter .......................................................................... 27 3.8.1 adc timing .................................................................................................... 27 3.8.2 setting of the adc reference voltages ........................................................... 28 3.8.3 non-linear and linear conversion mode ? ?gamma? correction .................. 29 3.8.4 pins involved in the adc circuitry ................................................................ 30 3.9 e lectronic shutter types ................................................................................ 31 3.9.1 rolling (curtain) shutter................................................................................. 31
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 3 of 67 3.9.2 snapshot (synchronous) shutter ..................................................................... 32 3.10 s equencer ........................................................................................................ 33 3.10.1 internal registers ........................................................................................ 33 3.10.2 detailed description of the internal registers ............................................. 35 3.10.3 data interfaces ........................................................................................... 41 4 timing diagrams .............................................................................................. 43 4.1 t iming requirements ......................................................................................... 43 4.2 s ynchronous shutter : single slope integration ......................................... 44 4.3 s ynchronous shutter : pixel readout ............................................................ 45 4.3.1 basic operation .............................................................................................. 45 4.3.2 pixel output .................................................................................................... 46 4.4 s ynchronous shutter : multiple slope integration .................................... 47 4.5 r olling shutter operation .............................................................................. 48 4.6 w indowing in x- direction ................................................................................ 49 4.7 w indowing in y- direction ................................................................................ 50 4.8 i nitialization ( start up behaviour )................................................................ 50 5 pin list.................................................................................................................... 51 6 pad position and packaging..................................................................... 54 6.1 b are die ............................................................................................................... 54 6.2 ibis5-a-1300 in 84- pins lcc package ............................................................. 55 6.2.1 technical drawing of the 84-pins lcc package............................................ 55 6.2.2 bonding of the ibis5-a-1300 sensor in the 84-pins lcc package................ 57 6.2.3 die placement of the ibis5-a-1300 in the 84-pins lcc package ................. 58 6.3 c over glass ........................................................................................................ 59 6.3.1 monochrome sensor....................................................................................... 59 6.3.2 color sensor................................................................................................... 60 7 storage and handling................................................................................. 62 7.1 s torage conditions ........................................................................................... 62 7.2 h andling and solder precautions ................................................................. 62 8 ordering information ................................................................................ 64 appendix a: ibis5 evaluation system ...................................................... 65 appendix b: frequently asked questions ........................................... 66
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 4 of 67 1 introduction overview the ibis5-a-1300 is a solid state cmos image se nsor that integrates the functionality of complete analog image acquisiti on, digitizer and digital si gnal processing system on a single chip. this 1.3-mega pixel (1280 x 1024) cmos active pixel se nsor dedicated to industrial vision features both ro lling and snapshot shutter. full frame readout time is 36 ms (max. 27.5 fps), and readout speed can be boosted by windowed region of interest (roi) readout. high dynamic range scenes can be captured using the double and multiples slope functionality. the sensor is available in a monochr ome version or bayer (rgb) patterned color filter array. user programmable row and column start/ stop positions allow windowing down to 2x1 pixel window for digital zoom. sub sampling reduces resolution while maintaining the constant field of view and an increased frame rate. the analog video output of the pixel array is processed by an on-ch ip analog signal pipeline. d ouble sampling (ds) eliminates the fixed pattern noise. the programmable ga in and offset amplifier maps the signal swing to the adc input range. a 10-bit adc c onverts the analog data to a 10-bit digital word stream. the sensor uses a 3-wire serial-p arallel (spi) interface or a 16-bit parallel interface. it operates with a 3.3v power s upply and requires only one master clock for operation up to 40 mhz. it is housed in an 84-pin ceramic lcc package. the ibis5-a-1300 is designed taking into c onsideration interfacing requirements to standard video encoders. in addition to the 10- bit pixel data stream, the sensor outputs the valid frame, line and pixel sync signals needed for encoding. this datasheet allows the user to develop a camera system based on the described timing and interfacing.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 5 of 67 key features the main features of the image sensor are identified as: ? sxga resolution: 1280 by 1024 pixels. ? 6.7 m high fill factor square pixels (based on the high-fill factor active pixel sensor technology of fillfactory (us patent no. 6,225,670 and others)). ? peak qe x ff of 30%. ? optical format: 2/3? (8.6mm x 6.9mm). ? pixel rate of 40 mhz usi ng a 40 mhz system clock. ? optical dynamic range: 64db (1600:1) in single slope operati on and 80?100db in multiple slope operation. ? on-chip 10 bit, 40msamples/s adc. ? programmable gain and offset output amplifier. ? both rolling curtain shutte r and synchronous shutter. ? random programmable windowing and sub-sampling modes. ? low fixed pattern noi se (<0.5% rms). ? on-chip timing and cont rol logic sequencer. ? processing is done in a cmos 0. 35 m triple metal process. part number part number package monochrome/ color die glass lid ibis5-a-1300-m-1 cyii5sm1300aa-hbc (preliminary) 84 pins jlcc package* monochrome monochrome** ibis5-a-1300-m-2 cyii5sm1300aa-qbc (preliminary) 84 pins lcc package monochrome monochrome ibis5-a-1300-c-1 cyii5sc1300aa-hac (preliminary) 84 pins jlcc package color color*** ibis5-a-1300-c-2 cyii5sc1300aa-qac (preliminary) 84 pins lcc package color color * jlcc package for use in evaluation kits only. ** d263 is used as monochrome glass lid (see figure 36 for spectral transmittance). *** s8612 is used as color glass lid (see figure 37 for spectral transmittance). other packaging combinations ar e available upon special request.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 6 of 67 2 specifications 2.1 pixel characteristics table 1: pixel characteristics parameter specification remarks pixel architecture 4-transistor active pixel sensor allows for both roll ing and synchronous (snapshot) shutter. pixel size 6.7 m x 6.7 m resolution 1280 x 1024 the resolution and pixel size results in a 2/3? optical format. pixel rate 40 mhz using a 40 mhz system clock. shutter types - rolling - snapshot - continuous imaging. - triggered synchronous shutter with integration and readout separate in time. full frame rate 27.5 fps depending on shutter t ype and integration time. 2.2 electro-optical specifications 2.2.1 overview table 2: electro-optical specifications parameter specification remarks fpn (on chip corrected) < 0.2% rms synchronous (snapshot) shutter. rolling curtain shutter. prnu <10% p-p 2% rms. conversion gain 17.6 uv/electron @ output. output signal amplitude 1.1v 1.8v unity gain. maximum output si gnal amplitude. saturation charge 62.500 e- 592 v.m2/w.s average white light. 3.29 v/lux.s visible band only (180 lx = 1 w/m2). sensitivity 8.46 v/lux.s visible + nir (70 lx = 1 w/m2). peak qe * ff peak sr * ff >30% 0.16 a/w average qe*ff = 25-30%. average sr*ff = 0.12 a/w. see spectral response curve. dark current (@ rt) 7.22 mv/s or ~ 410 e-/s auto saturation time in the order of 150s. noise electrons < 40 e- synchronous shutter. rolling curtain shutter. s/n ratio 1600:1 (64 db) synchronous shutter. rolling curtain shutter.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 7 of 67 parameter specification remarks spectral sensitivity range 400 ? 1000 nm parasitic sensitivity < 1% i.e. sensitivity of the storage node during read out (after integration). optical cross talk 8% cross talk to the nearest neighbor. power dissipation 175 mwatt typical. 2.2.2 spectral response curve figure 1: spectral response curve figure 1 shows the spectral response characteri stic. the curve is measured directly on the pixels. it includes effects of non-sensitive areas in the pixel, e.g. interconnection lines. the sensor is light sensitive betwee n 400 and 1000 nm. the peak qe * ff is approximately 30% between 500 and 700 nm. in vi ew of a fill factor of 50%, the qe is thus larger than 60% between 500 and 700 nm.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 8 of 67 2.2.3 photo-voltaic response curve figure 2: photo-voltaic response curve figure 2 shows the pixel response curve in linear response mode. this curve is the relation between the electrons de tected in the pixel and the output signal. the voltage to electrons conversion gain of th e pixel is 17.6 v/electron. 2.3 features and genera l specifications table 3: features and general specifications feature specification/description electronic shutter types 1. rolling curtain shutter. 2. synchronous (snapshot) shutter. windowing (roi) implemented as scanning of lines/columns from an uploaded position. sub-sampling modes: ? x-direction ? y-direction 1:2 sub-sampling. sub-sampling patterns: a. xxooxxoo (for bayer pattern color filter) b. ooxxooxx (for baye r pattern color filter) c. xoxoxoxo d. oxoxoxox identical sub-sample patterns as x-direction.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 9 of 67 feature specification/description extended dynamic range in rolling shutter: normal (1) or double (2) slope. in synchronous shutter: 1, 2, 3 or 4 slopes. digital output 10 bit adc @ 40 msamples/s. programmable gain range x1 to x12, in 16 steps of approx. 1.5 db using 4-bits programming. programmable offset 128 steps (7 bit). supply voltage vdd image core supply: range from 3.3 v to 4.5 v analog supply: nominal 3.3 v digital: nominal 3.3 v logic levels 3.3 v (digital supply). operational temperature range 0c to 60c, with degrad ation of dark current. die size (with scribe lines) 10.1 mm by 9.3 mm (x by y). package 84 pins lcc. 2.4 electrical specifications 2.4.1 absolute maximum ratings table 4: absolute maximum ratings symbol parameter value unit vdd dc supply voltage -0.5 to 4.5 v v in dc input voltage -0.5 to 3.8 v v out dc output voltage -0.5 to 3.8 v i io dc current drain per pin; any single input or output. 50 ma t l lead temperature (5 seconds soldering). 350 c absolute ratings are those values beyond which damage to the device may occur. vdd = vddd = vdda (vddd is supply to digital circuit, vdda to analog circuit). 2.4.2 recommended operating conditions table 5: recommended operation conditions symbol parameter min typ max unit vddh voltage on hold switches. +3.3 +4.5 +4.5 v vddr_left highest reset voltage. +3.3 +4.5 +4.5 v vddc pixel core voltage. +2.5 +3.0 +3.3 v vdda analog supply voltage of the image core. +3.0 +3.3 +3.6 v vddd digital supply voltage of the image core. +3.0 +3.3 +3.6 v
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 10 of 67 symbol parameter min typ max unit gnda analog ground -0.5 0 +0.5 v gndd digital ground -0.5 0 +0.5 v gnd_ab anti-blooming ground. -0.5 0 +0.5 v t a commercial operating temperature. 0 30 60 c all parameters are characterized for dc conditions after thermal equilibrium has been established. unused inputs must always be tied to an appropriate logic level, e.g. either vdd or gnd. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit. 2.4.3 dc electrical characteristics table 6: dc electrical characteristics symbol characteristic condition min max unit v ih input high voltage 2.1 v v il input low voltage 0.6 v i in input leakage current v in = v dd or g nd -10 +10 a v oh output high voltage v dd =min; i oh = -100ma 2.2 v v ol output low voltage v dd =min; i oh = 100ma 0.5 v i dd maximum operating current system clock <= 40mhz 40 60 ma
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 11 of 67 3 architecture and operation in this part the most important blocks of the sensor are described in more detail. 3.1 floor plan x-addressing analog multiplexe r column amplifiers p ixel core p ixel output amplifier i mager cor e adc sequencer sensor y-lef t addressin g y-right addressing e xte r nal connection system clock 40 mhz reset sample select column output c figure 3: block diagram of the ibis5-a-1300 image sensor figure 3 shows the architecture of the ibis5-a-1300 image sensor . it consists basically of a pixel array, one x- and two y-addressing registers for the re adout in x- and y- direction, column amplifiers that correct for the fixed pattern noise, an analog multiplexer and an analog output amplifier. the left y-addressing register is used for readout operati on. the right y-addressing register is used for reset of pixel row(s): ? in multiple slope synchronous shutter mode , the right y-addressing register resets the whole pixel core with a lowered reset voltage. ? in rolling curtain shutter mode, the right y- addressing register is used for the reset pointer in single and double slope op eration to reset 1 pixel row. most of the signals for the image core are ge nerated by the on-chip sequencer. some basic signals (like start/stop integration, line and frame sync signals , etc?) have to be generated externally.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 12 of 67 a 10-bit adc is implemented on chip but electr ically isolated from the image core. the analog pixel output has to be routed to the analog adc input on the outside. 3.2 pixel 3.2.1 architecture the pixel architecture used in the ibis5-a-1300 is a 4-transistor pixe l as shown in figure 4. the pixel has been implemented using the high fill factor tec hnique as patented by fillfactory (us patent no. 6,225,670 and others). the 4t-pixel features a snapshot shutte r but can also emulate the 3t-pixel by continuously closing sampling sw itch m2. using m4 as a global sample transistor for all pixels enables the snapshot shutter mode. due to this pixel architecture integration during read out is not possible in synchronous shutter mode. 3.2.2 color filter array the ibis5-a-1300 can also be pr ocessed with a bayer rgb color pattern. pixel (0,0) has a green filter and is situated on a green-blue row. blue red green1 pixel 0,0 green2 blue red green1 green2 blue red green1 green2 figure 5: color filter arrangement on the pixels. green1 and green2 hav e a slight different spectral reset sample mux column output c m1 m2 m3 m4 figure 4: architecture of the 4t-pixel
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 13 of 67 response due to crosstalk from neighboring pixels. green1 pixels are located on a blue-green row, green2 pixels are located on a green-red row. figure 6 below shows the respons e of the color filter array as function of the wavelength. note that this response curve includes the optic al cross talk of the pi xels. a nir filter on the color glass lid is used as well (see 6.3.2 fo r response of the color glass lid) to preserve correct color information. figure 6: color filter response curve 3.3 frame rate the pixel rate for this sensor is high e nough to support a frame rate of >100 hz for a window size of 640 x 480 pixels (vga format). taking into account a row blanking time of 3.5 s (as baseline, see also 3.10.2.1.4), this re quires a minimum pixel rate of nearly 40 mhz. the final bandwidth of the column ampl ifiers, output stage etc. is determined by external bias resistors. with a nominal pixel rate of 40 mhz a full frame rate of a little more than 27 frames/s is obtained. the frame period of the ibis5-a-1300 sensor depends on the shutter type and can be calculated as follows: 3.3.1 rolling shutter => frame period = (nr. lines * (rbt + pixel peri od * nr. pixels))
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 14 of 67 with: nr. lines: number of lines read out each frame (y). nr. pixels: number of pixels read out each line (x). rbt: row blanking time = 3.5 s (typical). pixel period: 1/40 mhz = 25 ns. example: read out time of the full resolu tion at nominal speed (40 mhz pixel rate): => frame period = (1024 * (3.5 s + 25 ns * 1280)) = 36.4 ms => 27.5 fps. 3.3.2 snapshot shutter => frame period = tint + tread out = tint + (nr. lines * (rbt + pixel period * nr. pixels)) with: tint: integr ation (exposure) time. nr. lines: number of line s read out each frame (y). nr. pixels: number of pixels read out each line (x). rbt: row blanking time = 3.5 s (typical). pixel period: 1/40 mhz = 25 ns. example: read out time of the full resoluti on at nominal speed (40 mhz pixel rate) with an integration time of 1 ms: => frame period = 1 ms + (1024 * (3.5 s + 25 ns * 1280)) = 37.4 ms => 26.8 fps. 3.3.3 region-of-interest (roi) read out windowing can easily be achieved by uploading th e starting point of the x- and y-shift registers in the sensor registers (see 3.10) us ing the various interfaces. this downloaded starting point initiates the shift register in the x- and y-direction triggered by the y_ start (initiates the y-shift register) and the y_ clk (initiates the x-shift register) pulse. the minimum step size for the x-address is 2 (onl y even start addresses can be chosen) and 1 for the y-address (every line can be addresse d). the frame rate increases almost linearly when fewer pixels are read out . table 7 gives an overview of the achievable frame rates (in rolling shutter mode) with various roi dimensions. table 7: frame rate vs. resolution image resolution (x*y) frame rate [frames/s] frame readout time [ms] comment 1280 x 1024 27 36 full resolution. 640 x 480 100 10 roi read out. 100 x 100 1657 0.6 roi read out.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 15 of 67 3.4 image core operation this section describes the functional operati on of the image core signalling and supplies considerations. 3.4.1 image core operation and signalling y_start sample hold y_clock y-left addressin g y-right addressing bus_ a y_clock pixel row p ixel column x addressing column amplifiers bus_b sys_clock read-pointer y_start reset vddh vddr_left vddr_right vddreset vddc output amplifier pxl_out pixel a pixel b figure 7: image core figure 7 is a functional representation of the image core without sub-sampling and column/row swapping circuits. most of the involved signals are not available from the outside because they are generated by th e x-sequencer and ss-sequencer blocks. the integration of the pixels is controlled by internal signals such as reset, sample, hold are generated by the on-chip ss-sequencer that is controlled with the external signals s s _ start and s s _ stop . reading out the pixel array starts by applying a y_ start together with a y_ clock signal; internally this is fo llowed by a calibration sequence to calibrate the output amplifiers (during the row blanking time); signals necessary to do this calibration are generated by the on-chip x- sequencer. this calibration sequence takes typically 3.5 us and is necessary to remove fixed pattern no ise of the pixels and of the column amplifiers themselves by means of a double sampling tec hnique. after the row blanking time the pixels are fe d to the output amplifier. the pixel rate is equal to the
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 16 of 67 s ys _ clock frequency. 3.4.2 image core s upply considerations the image sensor has several supply voltages: v ddh is the voltage that controls the samp le switches and s hould always be the highest voltage that is applied to the chip. the v ddr_left voltage is the highest (nominal) reset voltage of the pixel core. the v ddr_right voltage is generated from the v ddr_left voltage using a circuit that can be programmed with the k neepoint_lsb/msb bits in the sequencer register (see also 3.10.2.1.5). by setting the v ddr_right_ext bit in the s equencer register, the v ddr_right pin can be disconnected from the circuit and an external voltage can be applied to supply the multiple slope reset voltage. when no external voltage is applied (recommended) the v ddr_right pin should be connected to a capacitor (recommended value = 1f). v ddc is the supply of the pixel core. v dda is the analog supply of the image core and periphery. v ddd is the digital supply of th e image core and periphery. note that the ibis5-a-1300 image sensor has no power rejection circ uitry on-chip. as a consequence all variations on the analog s upply voltages can contribute to random variations (noise) on the analog pixel signal, wh ich is seen as random noise in the image. during the camera design precautions have to be taken to supply the sensor with very stable supply voltages to a void this additional noise. 3.4.2.1 snapshot shutter supply considerations when using the ibis5-a-1300 sensor in sn apshot shutter mode only the recommended supply voltage setti ngs are listed below in table 8. table 8: snapshot shutter recommended supply settings symbol parameter typ unit vddh voltage on hold switches. +4.5 v vddr_left highest reset voltage. +4.5 v vddc pixel core voltage. +3.3 v vdda analog supply voltage of the image core. +3.3 v vddd digital supply voltage of the image core. +3.3 v gnda analog ground. 0 v gndd digital ground. 0 v gnd_ab anti-blooming ground. 0 v
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 17 of 67 3.4.2.2 dual shutter supply considerations with the supply settings listed in table 8 some fixed column non-uniformities (fpn) can be seen when operating in rolling shutter m ode. if a dual shutter mode (both rolling and snapshot shutter) is re quired during operation one need to apply the supply settings listed in table 9 below to achieve the best possible image quality. table 9: dual shutter recommended supply settings symbol parameter typ unit vddh voltage on hold switches. +4.5 v vddr_left highest reset voltage. +4.5 v vddc pixel core voltage. +3.0 v vdda analog supply voltage of the image core. +3.3 v vddd digital supply voltage of the image core. +3.3 v gnda analog ground. 0 v gndd digital ground. 0 v gnd_ab anti-blooming ground. 0 v 3.4.3 image core biasing signals table 10 summarizes the biasing signals re quired to drive the ibis5-a-1300. for optimizations reasons with respect to speed and power dissipation of all internal block several biasing resistors are needed. table 10: overview of bias signals signal comment related module dc-level dec_cmd connect to vdda with r = 50k ? and decouple to gnda with c = 100 nf. decoder stage. 1.0 v dac_vhigh connect to vdda with r = 0 ? . high level of dac. 3.3 v dac_vlow connect to gnda with r = 0 ? . low level of dac. 0.0 v amp_cmd connect to vdda with r = 50k ? and decouple to gnda with c = 100 nf. output amplifier stage. 1.2 v col_cmd connect to vdda with r = 50k ? and decouple to gnda with c = 100 nf. columns amplifiers stage. 1.0 v pc_cmd connect to vdda with r = 25k ? and decouple to gnda with c = 100 nf. pre-charge of column busses. 1.1 v adc_cmd connect to vdda with r = 50k ? and decouple to gnda with c = 100 nf. analog stage of adc. 1.0 v adc_vhigh connect to vdda with r = 90 ? and decouple to gnda with c = 100 nf. high level of adc. 2.9 v adc_vlow connect to gnda with r = 360 ? and low level of adc. 1.4 v
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 18 of 67 signal comment related module dc-level decouple to gnda with c = 100 nf. each biasing signal determines the operation of a corresponding module in the sense that it controls the speed and power dissipation. the tolerance on the dc-level of the bias levels can vary +/- 150 mv due to process variations. 3.4.4 pins involved in the image core circuitry table 11 gives an overview of the ibis5-a-1300 pins used by the image core with a short functional description. power and ground lines are shared between the output amplifier and the image sensor.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 19 of 67 table 11: pins involved in the image core circuitry name no. function supply and ground connections vddc 7, 37 supply of the pixel core. vdda 8, 36 analog supply of the image core. gnda 9, 35 analog ground of the image core. gndd 10, 34 digital ground of the image core. vddd 11, 33 digital supply of the image core. gndab 51 anti-blooming ground. vddr_left 76 high level reset vddh 77 high supply voltage for hold switches in the image core. vddr_right 52 multiple slope reset voltage. digital controls y_start 14 (input) start frame read out. y_clock 15 (input) line clock. last_line 16 (output) generates a high level when the last line is read out. x_load 17 (input) loads new x-position during read out. sys_clock 18 (input) system (pixel) clock (max. 40mhz). pxl_valid 19 (output) pixel valid signal; high during row read out. ss_start 20 (input) start synchronous shutter operation. ss_stop 21 (input) stop synchronous shutter operation. time_out 22 (output) synchronous shutter: pulse when integration time is elapsed. can be used to trigger ss_stop although both signals can?t be tied together. rolling shutter: pulse when second y-sync appears sys_reset 23 (input) active high signal; have to be pulsed for minimal 5 clock cycles. all registers are set to 0 and sensor is put in a default state. sys_reset should be pulsed each time at start up of the sensor. eos_x 25 (output) diagnostic end of scan of x-register. reference voltages dec_cmd 13 decoder bias voltage. col_cmd 31 column amplifier bias. pc_cmd 32 pre-charge bias voltage.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 20 of 67 3.5 x-addressing because of the high pixel rate, the x-shift register selects 2 columns at the time for readout, so it runs at half the system clock speed. all even columns are connected to bus a; all odd columns to bus b. in the output am plifier, bus a and bus b are combined into one stream of pixel data at system clock speed. reg(n+1) reg(n+2) reg(n) x_sync x_sub ab ab column amplifiers b a bus_ a bus_b x_swap30 x_swap12 col(i) col(i+2) col(i+1) col(i+3) dec(n+1) dec(n+2) 1/2 sys_cloc k output amplifie r figure 8: column structure at the end of the row blanking time, the x _sync switch is closed while all other switches are open and the decoder output is fed to the register. the decoder loads a logical one in one of the registers and a logical zero in the rest. this defines the starting point of the window in the x direction. as soon as the x _sync signal is released, the register starts shifting from the start position. when no sub-sampling is required, x _sub is inactive. the pointer in the shift-register moves 1 bit at the time. when sub-sampling is enabled, x _sub is activated. the shift register moves 2 bits at the time. taking into account that every register selects 2 columns, hence 2 pixels, sub-sampling resu lts in the pattern ?xxooxxoo? when 8 pixels are considered.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 21 of 67 suppose the columns are numbered from left to right starting with 0 (zero) and sub- sampling is enabled: ? if columns 1 and 2, 5 and 6, 9 and 10 ? are swapped using the swap_12 switches, a normal sub-sampling patte rn of ?xoxoxoxo? is obtained. ? if columns 3 and 4, 7 and 8, 11 and 12 ? are swapped using the swap_30 switches, the pattern is ?oxoxoxox?. ? if both the swap_12 and swap_30 switche s are closed, patt ern ?ooxxooxx? is obtained. table 12: x-sub sample patterns x_sub x_swap12 x_swap30 sub sample pattern 0 0 0 xxxxxxxx 1 0 0 xxooxxoo 1 1 0 xoxoxoxo 1 0 1 oxoxoxox 1 1 1 ooxxooxx because every register addresses 2 columns at the time, the addressable pixels range in sub-sample mode is from 0 to half the maxi mum number of pixels in a row (only even values!). for instance: 0, 2, 4, 6, 8? 638.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 22 of 67 3.6 y-addressing for symmetry reasons, the sub-sampling modes in the y-direction are the same as in x- direction. reg(n) reg(n+1) reg(n+2) reg(n+3) reg(n+4) y_swap12 srh srh srh srh row(n+1) row(n+2) row(n+3) row(n+4) y_swap30 y_sync y_sub dec(n+1) dec(n+2 ) dec(n+3 ) dec(n+4 ) figure 9: row structure table 13: y-sub sample patterns y_sub y_swap12 y_swap30 sub-sample pattern 0 0 0 xxxxxxxx 1 0 0 xxooxxoo 1 1 0 xoxoxoxo 1 0 1 oxoxoxox 1 1 1 ooxxooxx in normal mode the pointer for the pixel row is shifted one at the time. when sub-sampling is enabled, y _sync is activated. the y-shift register shifts 2 succeeding bits and skips the 2 next bits . this results in pattern "xxooxxoo". activating y_swap12 results in pattern "xoxoxoxo". activating y_swap30 results in pattern "oxoxoxox". activating both y_swap12 and y_swap30 results in pattern "ooxxooxx". the addressable pixels range when y-sub sampling is enabled is: 0-1, 4-5, 8-9, 12-13, ? 1020-1021.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 23 of 67 3.7 output amplifier 3.7.1 architecture and settings the output amplifier stage is user-programmable for gain and offset level. gain is controlled by 4-bit wide word; offset by a 7-bit wide word. gain settings are on an exponential scale. offset is controlled by a 7-bit wide dac, which selects the offset voltage between 2 re ference voltages (d ac_vhigh & d ac_vlow ) on a linear scale. the amplifier is designed to match the specifi cations of the output of the imager array. this signal has a data rate of 40 mhz a nd is located between 1.17v and 2.95v. the output impedance of the amplifier is 260 ? . the output signal has a range between 1.17v a nd 2.95v, depending on the gain and offset settings of the amplifier. at unity gain and with a mid-range offset value the amplifier outputs a signal in between 1.59 v (light) a nd 2.70 v (dark). this analog range should fit to the input range of the adc, external or internal. the output swing in unity gain is approximately 1.11v and maximum 1.78v at the highest gain settings. figure 10: output structure figure 10 shows the architect ure of the output amplifier. the odd and even column amplifiers sample both pixel and reset value to perform a double sampling fpn - correction. there are 2 different offsets that can be adjusted using the on-chip dac (7 bit): d ac_fine and d ac_raw . d ac_fine is used to tune the difference between odd and even columns; d ac_raw is used to add a general (both even and odd columns) to the a gain [0?3] unity gain 1 s r s r odd even + + dac_vhigh dac_vlow dac_raw [6:0] dac_fine [6:0] dac_raw dac_fine pxl_out
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 24 of 67 fpn corrected pixel value. this pixel value is fed to the first amplifier stage which has an adjustable gain, controlled by a 4-bit word (?gain [0?3]?). after this, a unity feedback amplifier buffers the signal and the signal leaves the chip. this 2 nd amplifier stage determines the maximal r eadout speed, i.e. the bandwidth and the slew rate of the output signal. the whole ampl ifier chain is designed for a data rate of 40 mpix/s (@20 pf). 3.7.2 output amplifier gain control the output amplifier gain is cont rolled by a 4-bit word set in the a mplifier register (see section 3.10.2.8). an overview of the gain settings is given in table 14. table 14: overview gain settings bits dc gain bits dc gain 0000 1.37 1000 6.25 0001 1.62 1001 7.89 0010 1.96 1010 9.21 0011 2.33 1011 11.00 0100 2.76 1100 11.37 0101 3.50 1101 11.84 0110 4.25 1110 12.32 0111 5.20 1111 12.42 3.7.3 setting of the dac reference voltages in the output amplifier, the offset can be trimmed by loading registers d acraw_reg and d acfine_reg . d ac_raw is used to adjust the offs et of the output amplifier and d ac_fine is used to tune the offset between the even and odd columns. these registers are inputs for 2 dacs (see fi gure 10) that operate on the same resistor that is connected between pins d ac_vhigh and d ac_vlow . the range of the dac is defined using a resis tive division with r vhigh , r dac and r vlow .
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 25 of 67 r dac_vhigh dac_vlow = 0 v dac_vhigh = 3.3 v r dac_vlow r dac external internal external 7.88 k ? internal figure 11: in- and external dac connections the internal resistor r dac has a value of approximately 7.88 k ? . the recommend resistor values for both dac_vlow and dac_vhigh are 0 ? . 3.7.4 pins involved in the output amplifier circuitry table 15 gives an overview of the ibis5-a-1300 pins used by the output amplifier with a short functional description. power and ground lines are shared between the output amplifier and the image sensor.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 26 of 67 table 15: pins involved in the output amplifier circuitry name no. function analog signals pxl_out1 28 analog output signal to be connected to the input of the adc (adc_in, pin 69) pxl_out2 29 analog output signal to be connected to the input of the adc (adc_in, pin 69) note : 2 outputs were designed for debugging reasons but it seemed not necessary. it is possible to use them both if you want to send even and odd pixels (or lines) to 2 outputs. there is no speed gain when using 2 outputs because the 2 outputs run at a halved output rate (20mhz). it recommended to use only one analog output (connect pxl_out1 to adc_in). digital controls el_black 24 active high digital input. when this signal is pulsed a hardwar e black level is fed to the output amplifier instead of the normal pixel values. the hardware black level can be changed by the dac_raw register. reference voltages dac_vhigh 26 high reference voltage of the dac. dac_vlow 27 low reference voltage of the dac. amp_cmd 30 output amplifier speed/power bias voltage. can be used to enhance the speed of the output stage.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 27 of 67 3.8 analog to digital converter the ibis5-a-1300 has a 10 bit flash analog digital converter running nominally at 40 msamples/s. the adc is electrically separate d from the image sensor. the input of the adc (a dc_in ; pin 69) should be tied externally to the output (p xl_out1 ; pin 28) of the output amplifier. table 16: adc specifications input range 1 ? 3v (*) quantization 10 bits nominal data rate 40 msamples/s dnl (linear conversion mode) typ. < 0.5 lsb inl (linear conversion mode) typ. < 3 lsb input capacitance < 20 pf power dissipation @ 40 mhz typ. 45 ma * 3.3v = 150 mw conversion law linear / gamma-corrected (*): the internal adc range will be typically 100mv lower then the external applied a dc_vhigh and a dc_vlow voltages due to voltage dr ops over parasitic internal resistors in the adc. 3.8.1 adc timing at the rising edge of s ys _ clock the next pixel is fed to the input of the output amplifier. due to internal delays of the s ys _c lock signal it takes approximately 20 ns before the output amplifier outputs the analog value of the pixel as shown in figure 12. the adc converts the pixel data on the rising edge of the a dc_clock but it takes 2 clock cycles before this pixel data is at the output of the adc. this pipeline delay is shown in figure 12. due to these delays it is advised that a va riable phase difference is foreseen between the a dc _ clock and the s ys _ clock to tune the optimal sample moment of the adc. figure 12: adc timing
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 28 of 67 3.8.2 setting of the adc reference voltages r adc_vhigh a dc_vlow ~ 1.4 v a dc_vhigh ~ 2.9 v r adc_vlow r adc externa l interna l externa l figure 13: in- and external adc connections the internal resistor r adc has a value of approximately 385 ? . this results in the following values for the external resistors: resistor value ( ? ) r adc_vhigh 90 r adc 385 r adc_vlow 360 note that the recommended adc resistors valu e yields in a conversion of the full analog output swing at unity gain (v dark_analog < adc_vhigh and v light_analog > adc_vlow). the values of the resistors depend on the value of r adc . the voltage difference between a dc_vlow and a dc_vhigh should be at least 1.0v to assure proper working of the adc.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 29 of 67 3.8.3 non-linear and li near conversion mode ? ?gamma? correction figure 14: linear and non-linear adc conversion characteristic figure 14 shows the adc transfer charact eristic. the non-linear (exponentional) adc conversion is intended for gamma -correction of the images. it increases contrast in dark areas and reduces contrast in bright areas. the non-linear tr ansfer function is given by: vin = a dc_vhigh + (a dc_vhigh ?a dc_vlow ) * with: a=5 b=0.027 x=digital output code a*x + b*x 2 a*1023+b*1023 2
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 30 of 67 3.8.4 pins involved in the adc circuitry table 17 gives an overview of the ibis5-a-1 300 pins involved in the adc circuitry. table 17: pins involved in the adc circuitry name no. description analog signals adc_in 69 input, connect to sensor?s output (pxl_out1; pin 28) digital controls adc_clock 58 (input) adc clock; adc converts on rising edge. digital output adc_out<9>..<0> 59?68 output bits; <0> = lsb, <9> = msb reference voltages adc_vhigh 75 adc high reference voltage adc_vlow 53 adc low reference voltage adc_cmd 70 adc speed/power bias voltage. power & ground adc_vddd 57, 71 adc digital supply (3.3v) adc_gnda 54, 72 adc analog ground (0.0v) adc_gndd 56, 73 adc digital ground (0.0v) adc_vdda 55, 74 adc analog supply (3.3v)
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 31 of 67 3.9 electronic shutter types the ibis5-a-1300 has 2 different shutter types: a rolling (curtain) shutter and a snapshot (synchronous) shutter. 3.9.1 rolling (curtain) shutter the name is due to the fact that the effect is similar to a curtain shutter of a slr film camera. although it is a pure electronic opera tion, the shutter seems to slide over the image. a rolling shutter is easy and elegant to implement in a cmos sensor. as can be seen in figure 15, there are two y shift regist ers. one of them points to the row that is currently being read out. the other shift regist er points to the row that is currently being reset. both pointers are shifted by the same y-clock and move over the focal plane. the integration time is set by the delay between both pointers. reset line read line x y x y time axis line number reset sequence frame time integration time figure 15: rolling shutter operation
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 32 of 67 in figure 15, we schematically indicate the relative shift of the integration times of different lines during the rolling shutter opera tion. each line is read and reset in a sequential way. the integration time is the same for all lines, but is shifted in time. the integration time can be varied through the i nt _ time register (in number of lines). this indicates us that all pi xels are light sensitive at a nother period of time, which can cause some blurring if a fast moving object is captured. when the sensor is set to rolling shutter mode, the input s s_start and s s_stop should best be held low. 3.9.2 snapshot (synchronous) shutter a synchronous (global, snapshot) shutter solv es that inconvenience. light integration takes place on all pixels in parallel, al though subsequent rea dout is sequential. time axis line number integration time burst readout time common reset common sample&hold flash could occur here figure 16: synchronous shutter operation figure 16 shows the integration and read out sequence for the sync hronous shutter. all pixels are light sensitive at the same peri od of time. the whole pixel core is reset simultaneously and after the integration time al l pixel values are sampled together on the storage node inside each pixel. the pixel core is read out line by line after integration. note that the integration and read out cycle is carry out in serial , which causes that no integration is possible during read out. during synchronous shutte r the input pins s s_start and s s_stop are used to start and
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 33 of 67 stop the synchronous shutter. 3.10 sequencer figure 7 showed a number of control signals th at are needed to operate the sensor in a particular sub-sampling mode, with a certain integration time, output amplifier gain, etc. most of these signals are generated on chip by the sequencer that uses only a few control signals. these control signals should be generated by the external system: ? s ys _ clock (x-clock), which will define the pixel rate, ? y _start pulse, which will indicate the start of a new frame, ? y _clock , which will select a new row and will start the row blanking sequence, including the synchronization and loading of the x-register. ? s s _ start and s s _ stop to control the integration pe riod in snapshot shutter mode. the relative position of the pu lses will be determined by a number of data bits that are uploaded in internal registers through the serial or parallel interface. 3.10.1 internal registers table 18 shows a list of the internal registers wi th a short description. in the next section, the registers are explained in more detail. table 18: internal registers register bit name description 11:0 sequencer register default value <11:0>:?000011000100? 0 shutter_type 1 = rolling shutter 0 = synchronous shutter 1 frame_cal_mode 0 = fast 1 = slow 2 line_cal_mode 0 = fast 1 = slow 3 cont_charge 1 = ?continuous? precharge enabled. 4 gran_x_seq_lsb 5 gran_x_seq_msb granularity of the x sequencer clock 6 gran_ss_seq_lsb 7 gran_ss_seq_msb granularity of the ss sequencer clock 8 kneepoint_lsb 9 kneepoint_msb sets reset voltage for multiple slope operation. 10 kneepoint_enable 1 = enables multiple slope operation in synchronous shutter mode 0 (0000) 11 vddr_right_ext 1 = disables circuit that generates vddr_right voltage so external voltage can be applied. 1 (0001) 11:0 nrof_pixels number of pixels to count (maximum 1280/2).
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 34 of 67 register bit name description default value <11:0>:?001001111111? 2 (0010) 11:0 nrof_lines number of lines to count. default value <11:0>:?001111111111? 3 (0011) 11:0 int_time integration time. default value <11:0>:?111111111111? 4 (0100) 10:0 x_reg x start position (maximum 1280/2). default value <10:0>:?00000000000? 5 (0101) 10:0 yl_reg y-left start position. default value <10:0>:?00000000000? 6 (0110) 10:0 yr_reg y-right start position . default value <10:0>:?00000000000? 7:0 image core register default value <7:0>:?00000000? 0 test_even test even columns. 1 test_odd test odd columns. 2 x_subsample enable sub-sampling in x-direction. 3 x_swap12 swap columns 1-2, 5-6, ? 4 x_swap30 swap columns 3-4, 7-8, ? 5 y_subsample enable sub-sampling in y-direction. 6 y_swap12 swap rows 1-2, 5-6, ? 7 (0111) 7 y_swap30 swap rows 3-4, 7-8, ? 6:0 amplifier register default value <6:0>:?1010000? 0 gain<0> 1 gain<1> 2 gain<2> 3 gain<3> output amplifier gain setting. 4 unity 1 = amplifier in unity gain mode. 5 dual_out 1 = activates second output. 8 (1000) 6 standby 0 = amplifier in standby mode. 9 (1001) 6:0 dacraw_reg amplifier dac raw offset. default value <6:0>:?1000000? 10 (1010) 6:0 dacfine_reg amplifier dac fine offset. default value <6:0>:?1000000? 2:0 adc register default value <2:0>:?011? 0 tristate_out 0 = output bus in tri-state. 1 gamma 0 = gamma-correction on. 11 (1011) 2 bit_inv 1 = bit inversion on output bus. 12 (1100) reserved. 13 (1101) reserved. 14 (1110) reserved. 15 (1111) reserved.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 35 of 67 3.10.2 detailed description of the internal registers 3.10.2.1 sequencer register (7:0) 3.10.2.1.1 shutter type (bit 0) the ibis5-a-1300 image sens or has 2 shutter types: 0 = synchronous shutter. 1 = rolling shutter. 3.10.2.1.2 output amplifie r calibration (bits 1 and 2) bits f rame_cal_mode and l ine_cal_mode define the calibration mode of the output amplifier. during every row-blanking period, a calibration is done of the output amplifier. there are 2 calibration modes. the f ast mode (= 0) can force a calibration in one cycle but is not so accurate and suffers fr om ktc noise, while the s low mode (= 1) can only make incremental adjustments and is noise free. approximately 200 or more ?slow? calibrations will have the same effect as 1 ?fast? calibration. different calibration modes can be se t at the beginning of the frame (f rame_cal_mode bit) and for every subsequent line that is read (l ine_cal_mode bit). the beginning of a frame is defined by the y _start input (see lower), y_ clock defines the beginning of a new row. 3.10.2.1.3 continuous charge (bit 3) for some applications it might be necessar y to use continuous charging of the pixel columns instead of a pre-charge on every line sample operation. setting bit c ont_charge to ?1? will activate this function. the resistor connected to pin p c_cmd is used to control the current level on every pixel column. 3.10.2.1.4 internal clock gran ularities (bits 4, 5, 6 and 7) the system clock is divi ded several times on chip. the x-shift-register that cont rols the column/pixel readout, is clocked by half the system clock rate. odd and even pixel columns are sw itched to 2 separate buses. in the output amplifier the pixel signals on the 2 buses are co mbined into one pixel stream at the same frequency as s ys _ clock . the clock, that drives the ?snapshot? or synchronous shutter sequencer, can be programmed using the bits g ran_ss_seq_msb (bit 7) and g ran_ss_seq_lsb (bit 6). this way the integration time in synchronous shutter mode can be a multiple of 32, 64, 128 or 256 times the system clock period. to overcome global reset issues it is advised
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 36 of 67 that the longest ss granularity is used (bits 6&7 set to ?1?). table 19: ss sequencer clock granularities gran_ss_seq_msb/lsb ss-sequencer clock integration time step* 00 32 x sys_clock 800 ns 01 64 x sys_clock 1.6 us 10 128 x sys_clock 3.2 us 11 256 x sys_clock 6.4 us * using a sys_clock of 40 mhz (25 ns period) the clock that drives the x-sequencer can be a multiple of 4, 8, 16 or 32 times the system clock. clocking the x-sequen cer at a slower rate (longer row blanking time; pixel read out speed is always equal to the s ystem_clock ) can result in more signal swing for the same light conditions. table 20: x sequencer clock granularities gran_x_seq_msb/lsb x-sequencer clock row blanking time* 00 4 x sys_clock 3.5 us 01 8 x sys_clock 7 us 10 16 x sys_clock 14 us 11 32 x sys_clock 28 us * using a sys_clock of 40 mhz (25 ns period) 3.10.2.1.5 pixel reset knee- point for multiple slope ope ration (bits 8, 9 and 10) in normal (single slope) mode the pixel reset is controlled from the left side of the image core using the volta ge applied on pin v ddr_left as pixel reset voltage. in multiple slope operation one or more variable pixel reset vol tages have to be applied. bits k nee_point_msb and k nee_point_lsb select the on chip-generated pixel reset voltage. bit k nee_point_enable set to ?1? switches control to the right side of the image core so the pixel reset voltage (v ddr _ right ), selected by bits k nee_point_msb/lsb , is used. bit k nee_point_enable should only be used for multiple slope operation in synchronous shutter mode. in rolling shutter mode, only the bits k nee_point_msb/lsb must be used to select the sec ond knee-point in dual slope operation. table 21: multiple slope register settings knee_point msb/lsb enable (1) pixel reset voltage (v) vddr_right knee-point (v) 00 0 or 1 vddr_left 0 01 1 vddr_left ? 0.76 + 0.76 10 1 vddr_left ? 1.52 + 1.52 11 1 vddr_left ? 2.28 + 2.28 the actual knee-point depends on v ddh , v ddr_left and v ddc applied to the sensor.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 37 of 67 3.10.2.1.6 external pixel reset voltage for multiple slope (bit 11) when bit v ddr_right_ext is set to ?1?, the circuit that generates the variable pixel reset voltage is disabled and the volta ge externally applied to pin v ddr_right is used as the double/multiple slope reset voltage. when bit v ddr_right_ext is set to ?0? the variable pixel reset voltage (used for multiple slope operation) can be monitored on pin v ddr_right . 3.10.2.2 n rof_pixels register (11:0) after the internal x_sync is gene rated (start of the pixel rea dout of a particular row), the p ixel_valid signal goes high. the p ixel_valid signal goes low when the pixel counter reaches the value loaded in the n rof _ pixel register. due to the fact that 2 pixels are read at the same clock cycle this num ber have to be divided by 2 (n rof_pixels = (width of roi / 2) - 1). 3.10.2.3 n rof_lines register (11:0) after the internal yl_sync is generate d (start of the frame readout with y _start ), the line counter increases with each y _clock pulse until it reaches th e value loaded in the n rof _ lines register and an l ast_line pulse is generated. 3.10.2.4 int_time register (11:0) the i nt_time register is used to set the integration time of the electronic shutter. the interpretation of the i nt_time depends on the chosen s hutter type (rolling or synchronous). synchronous shutter after the s s_start pulse is applied an internal counter counts the number of ss granulated clock cycles until it reaches the value loaded in the i nt_time register and a t ime_out pulse is generated. this t ime_out pulse can be used to generate the s s_stop pulse to stop the integration. when the i nt_time register is used the maximum integration time is: t int_max = 2 12 * 256 (maximum granularity) * (40 mhz) -1 = 26.2 ms. this maximum time can be increased if an external counter is used to trigger s s_stop . the minimal value that should be loaded into the i nt_time register is 10 (see also 3.10.2.1.4). rolling shutter when the y _start pulse is applied (start of the frame readout), the sequencer will generate the yl_sync pulse for the left y-shift register (read out y-shift register). this loads the left y-shift register with the pointer loaded in y l _ reg register. at each y_clock pulse, the pointer shifts to the next row and the integration time counter increases until it reaches the value loaded in the i nt _ time register. at that moment, the
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 38 of 67 yr_sync pulse for the right y- shift register is generated which loads the right y-shift register (reset y-shift register) with the pointer loaded in y r _ reg register ( figure 17 ). the integration time counter is reset when the s ync for the left y-shift register is asserted. both shift registers keep moving unt il the next sync is asserted (y _start for the left y- shift register and the sync for the right y-shif t register is generated when the integration time counter reaches the i nt_time value). sync of left shift-register sync of right shift-register l ine n t reg_int l ast line, followed by sync of left shift-register t int sync figure 17: synchronization of the shift registers in rolling shutter mode. t reg_int difference between left and right pointer = value set in the i nt _ time register (number of lines). the actual integration time is given by: t int integration time [# lines] = n rof _ lines register - i nt _ time register 3.10.2.5 x_reg register (10:0) the x_ reg register determines the st art position of the window in the x-direction. in this direction, there are 640 possible starting positions (2 pixels ar e addressed at the same time in one clock cycle). if sub sampling is enabled only the even pixels ca n be set as starting position (for instance: 0, 2, 4, 6, 8? 638). 3.10.2.6 yl_reg (10:0) and yr_reg (10:0) the y l _ reg and yr_reg registers determine the start po sition of the window in the y- direction. in this direction, there are 1024 possible starting positi ons. in rolling shutter mode the y l_reg register sets the star t position of the read (l eft) pointer and the y r_reg sets the start position of the reset (ri ght) pointer. for both shutter types y l _ reg should always be equal to yr_reg. 3.10.2.7 image core register (7:0) bits 1:0 of the i mage _ core register define the test mode of the image core. setting 00 is the default and normal operation mode. in case the bit is set to 1, the odd (bit 1) or even (bit 0) columns are tight to the reset level. if the internal adc is used bits 0 and 1 can be used to create test pattern to test the sample moment of the adc. if the adc sample moment is not chosen correctly the created te st pattern will not be black-white-black-etc.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 39 of 67 (i mage _ core register set at 1 or 2) or bl ack-black-white-wh ite-black-black (i mage _ core register set at 9) but grey shadings if the se nsor is saturated. see also paragraph 3.8.10 for detailed adc timing. bits 7:2 of the i mage _ core register define the sub-sampli ng mode in the x-direction (bits 4:2) and in the y-direction (bits 7:5). the sub-sampling modes and corresponding bit setting are given in table 12 (secti on 3.5) and table 13 (section 3.6). 3.10.2.8 amplifier register (6:0) 3.10.2.8.1 g ain (bits 3:0) the gain bits determine the gain setting of th e output amplifier. they are only effective if u nity = 0. the gains and corresponding bit sett ing are given in table 14 section 3.7.2). 3.10.2.8.2 u nity (bit 4) in case u nity = 1, the gain setting of g ain is bypassed and the gain amplifier is put in unity feedback. 3.10.2.8.3 d ual_out (bit 5) if d ual_out = 1, the two output amplifiers are active. if d ual_out = 0, the signals from the two busses are multiplexed to output p xl_out1 which should be connected to a dc_in . the gain amplifier and output driver of the second path are put in standby. 3.10.2.8.4 s tandby if standby = 0, the complete output amp lifier is put in standby. for normal use s tandby should be set to 1. 3.10.2.9 dac_raw register (6:0) and dac_fine (6:0) register these registers determine the black reference le vel at the output of the output amplifier. bit setting 1111111 for d ac _ raw register gives the highest offset voltage, bit setting 0000000 for d ac _ raw register gives the lowest offset voltage. ideally, if the two output paths have no offset mismatch, the d ac _ fine register must be set to 1000000. deviation from this value can be used to compen sate the internal mismatch (see 3.7). 3.10.2.10 adc register (2:0) 3.10.2.10.1 t ristate_out (bit 0) in case t ristate = 0, the adc_d<9:0> outputs are in tri-state mode. t ristate = 1 for normal operation mode. 3.10.2.10.2 g amma (bit 1) if g amma is set to 1, the adc input to output conversion is linear; otherwise the
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 40 of 67 conversion follows a ?gamma? law (more cont rast in dark parts of the window, lower contrast in the bright parts). s ee section 3.8.3 for more details. 3.10.2.10.3 b it_inv (bit 2) if b it_inv = 1, 0000000000 is the conversion of th e lowest possible input voltage, otherwise the bits are inverted.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 41 of 67 3.10.3 data interfaces 2 different data interfaces are implemente d. they can be selected using pins i f_mode (pin 12) and s er_mode (pin 6). table 22: serial and parallel interface selection if_mode ser_mode selected interface 1 x parallel 0 1 serial 3 wire 0 0 no mode selected. 3.10.3.1 parallel interface the parallel interface uses a 16-bit parallel input (p_ data <15:0>) to upload new register values. asserting p_ write will load the parallel data into the internal register of the ibis5-a-1300 where it is decoded. figure 18: parallel interface timing p _data (15:12) address bits r eg_addr (3:0) p _data (11:0) data bits r eg_data (11:0) 3.10.3.2 serial-3-wire interface the serial-3-wire interface (or se rial-to-parallel interface) uses a serial input to shift the data in the register buffer. when the complete data word is shifted into the register buffer the data word is loaded into the internal register where it is decoded.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 42 of 67 figure 19: serial-3 ?wire interface timing s _data (15:12) address bits r eg_addr (3:0) s _data (11:0) data bits r eg_data (11:0) when s_ en is asserted the parallel da ta is loaded into the internal registers of the ibis5- a-1300. the maximum tested frequency of s _data is 2.5 mhz. 3.10.3.3 pins involved in the interface circuitry table 23: pins involved in the interface circuitry name no. function digital controls p_data<0>?<7> 38-45 data parallel interface. <0> : lsb p_data<15>?<9> 78-84 data parallel interface. <15> : msb p_data<8> 1 date parallel interface. si2_addr<0>?<4> 46-50 2 wire serial address bits (7 bits). <0>:lsb <4>:msb bits 4,5 and 6 are tied together. p_wr 2 parallel write. s_clk 3 clock serial interface. s_data 4 data serial interface. s_en 5 enable serial interface. ser_mode 6 serial mode: 0 = disable; 1 = serial-3-wire enabled.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 43 of 67 4 timing diagrams 4.1 timing requirements there are 6 control signals th at operate the image sensor: ? s s_start ? s s_stop ? y _clock ? y _start ? x _load ? s ys _ clock these control signals should be generated by the external system with following time constraints to s ys_clock ( rising edge = active edge): ? t setup >7.5 ns. ? t hold > 7.5 ns. it is important that these signals are free of any glitches. figure 20: relative timing of the 5 sequencer control signals figure 22 shows a recommended schematic for generating the basic signals and to avoid any timing problems. ff sys_clock_n sys_clock ss_start ss_stop y_clock y_start x_load figure 21: recommended schematic for generating basic signals
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 44 of 67 4.2 synchronous shutter: single slope integration figure 22: synchronous shutter: single slope integration s s_start and s s_stop should change on the falling edge of the s ys_clock ( tsetup and thold > 7.5 ns). the pulse width of both signals should be minimum 1 s ys _ clock cycle. as long as s s_start or s s_stop are asserted, the sequencer stays in a suspended state. t 1 time counted by the integrati on timer until the value of i nt_time register is reached. the integration timer is clocke d by the granulated ss-sequencer clock. t 2 t ime_out signal stays high for 1 granulat ed ss-sequencer clock period. t 3 there are no constraints for this time. the user can use the t ime_out signal to trigger the s s_stop pin (or use an external counter to trigger s s_stop) although that both signal can?t be tied together. t 4 during this time, the ss-sequencer applies the control signals to reset the image core and start integration. this takes 4 granulated ss-sequencer clock periods. the integration time counter star ts counting at the first risi ng edge after the falling edge of s s_start . t 5 the ss-sequencer puts the image core in a readable state. it takes 2 granulated ss- sequencer clock periods. t int the ?real? integration or exposure time.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 45 of 67 4.3 synchronous shutter: pixel readout 4.3.1 basic operation figure 23: synchronous shutter: pixel read out y _start and y _clock should change on the falling edge of the s ys_clock ( tsetup and thold > 7.5 ns). the pulse width s hould be minimum 1 clock cycle for y _clock and 3 clock cycles for y _start . as long as y _clock is applied, the sequencer stays in a suspended state. t 1 row blanking time: during this period, the x-sequen cer generates the control signals to sample the pixel signal and pixel reset levels (double sampling fpn- correction), and start the readout of one li ne. the row blanking time depends on the granularity of the x-se quencer clock (see below). table 24: row blanking time as function of x-sequencer granularity granularity n gran t 1 (s) = 35 x n gran x t sys_clock gran_x_seq msb/lsb x 4 140 x t sys_clock = 3.5 00 x 8 280 x t sys_clock = 7.0 01 x 16 560 x t sys_clock = 14.0 10 x 32 1120 x t sys_clock = 28.0 11 t 2 pixels counted by pixel counter until the value of n rof_pixels register is reached. p ixel_valid goes high when the internal x _sync signal is generated, in other words when the readout of the pixels is started. p ixel_valid goes low when the pixel counter reaches th e value loaded in the n rof_pixels register (after a complete row read out). t 3 l ast_line goes high when the line counter reaches the value loaded in the n rof_lines register and stays high for 1 line peri od (until the next falling edge of y- clock ). on y _start the left y-shift-register of the image core is loaded with the yl-pointer that
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 46 of 67 is loaded in to register y l_reg. 4.3.2 pixel output figure 24: pixel output the pixel signal at the p xl_out1 output becomes valid after 5 s ys_clock cycles when the internal x _sync (= start of p ixel_valid output or external x _load pulse) pulse is asserted. t 1 row blanking time (see table 24). t 2 5 s ys_clock cycles. t 3 time for new x-pointer position upload in x _reg register (see 4.6 for more details).
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 47 of 67 4.4 synchronous shutter: multiple slope integration figure 25: multiple slope integration up to 4 different pixel reset voltages can be used during multiple slope operation in synchronous shutter mode. this is done by uploading new values to register bits k neepoint_msb/lsb/enable before a new s s_start pulse is applied. bit k neepoint_enable should be set high to do a pixel reset with a lower voltage. bits k neepoint_msb/lsb/enable should be set back to ?0? before the ss_stop pulse is applied. every time an s s_start pulse is applied, the integr ation time counter is reset. table 25: multiple slope register settings kneepoint msb/lsb enable initial setup 00 0 1 st register upload 01 1 2 nd register upload 10 1 3 th register upload 11 1 4 th register upload 00 0 the register upload should be uploaded after time t stable , otherwise the change will affect the ss-sequencer resulting in a bad pixel reset. t stable depends on the granularity of the ss-sequencer clock (see table 26). table 26: t stable for different granularity settings granularity n gran t stable ( s) = 5 x n gran x t sys_clock gran_ss_seq msb/lsb x 32 160 x t sys_clock = 4 00 x 64 320 x t sys_clock = 8 01 x 128 640 x t sys_clock = 16 10
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 48 of 67 granularity n gran t stable ( s) = 5 x n gran x t sys_clock gran_ss_seq msb/lsb x 256 1280 x t sys_clock = 32 11 t upload depends on the interface mode used to upload the registers table 27: t upload for different interface modes interface mode t upload ( s) parallel 1 serial 3 wire 8 (2.5 mhz clock rate) 4.5 rolling shutter operation figure 26: rolling shutter operation the integration of the light in the image sens or is done during readout of the other lines. the only difference with synchr onous shutter is that the t ime_out pin is used to indicate when the y _sync pulse for the right y-shift-register (r eset y-shift register) is generated. this loads the right y-shift-register with the pointer loaded in register y r_reg . the y _sync pulse for the left y-shift register (re ad y-shift register) is generated with y _start . the i nt_time register defines how many lines have to be counted before the y _sync of the right y-shift-register is generated, he nce defining the integration time. see also chapter?s 3.10.2 and 3.10.2.4 for a detailed description of the rol ling shutter operation. t int integration time [ # lines] = register(n rof_lines ) - register(i nt_time ) note : for normal operation the values of the y l_reg and y r_reg registers are equal.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 49 of 67 4.6 windowing in x-direction figure 27: windowing in the x-direction an x _load pulse overrides the internal x _sync signal, loading a new x-pointer (stored in the x _reg register) into the x-shift-register. the x _load pulse has to appear on the falling edge of s ys_clock and has to remain 2 s ys_clock cycles high overlappi ng 2 rising edges of s ys_clock . on one of the 2 rising edges of s ys_clock the new x-pointer is loaded. t load is the available time to upload the register and is defined from th e previous register load to the rising edge of x _load . it depends on the settling time of the register and the x-decoder. the actual time to load the re gister is self depends on the interface mode that is used. the parallel interface is the fastest. table 28: t load for different interfaces interface mode t load ( s) parallel interface 1 (about 40 sys_clock cycles) serial 3 wire 16 (at 2.5 mhz data rate)
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 50 of 67 4.7 windowing in y-direction figure 28: windowing in the y-direction a new y-pointer can be loaded into th e y-shift-register, by reapplying the y _start pulse after loading a new y-pointer value into the y l_reg and y r_reg registers. every time a y _start pulse appears, a frame calibration of the output amplifier is done. 4.8 initialization (start up behaviour) to avoid any high current c onsumption at start up it is recommended to apply the sys_clock signal as soon as possible after or even before power on of the image sensor. after power on of the image sensor it is recommended to apply sys_reset for minimal 5 sys_clock periods to assure a proper re set of the on-chip sequencer and timing circuitry. all internal register will be set to 0 after sys_reset is applied. as all the ibis5-a-1300 control signal are ac tive high it is also recommended to apply a low level (before sys_reset occurs) to thes e pins at start up to avoid latch up.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 51 of 67 5 pin list the ibis5-a-1300 image sensor is packaged in a leadless ceramic carrier (lcc package). table 29 is a list of all the pins and th eir function. in total, there are 84 pins. table 29: pin list pin pin name pin type pin description 1 p_data<8> input digital input. data parallel interface. 2 p_wr input digital input (active high). parallel write. 3 s_clk input digital input. clock signal of serial interface. 4 s_data input digital input/output. data of serial interface. 5 s_en input digital input (active low). enable of serial-3-wire interface. 6 ser_mode input digital input. serial mode enable (1=enable serial-3- wire, 0=disable). 7 vddc supply analog supply voltage. supply voltage of the pixel core [3.3v]. 8 vdda supply analog supply voltage. analog supply voltage of the image sensor [3.3v]. 9 gnda ground analog ground. analog ground of the image sensor. 10 gndd ground digital ground. digital ground of the image sensor. 11 vddd supply digital supply voltage. digital supply voltage of the image sensor [3.3v]. 12 if_mode input digital input. interface mode (1=parallel; 0=serial). 13 dec_cmd input analog input. biasing of decoder stage. connect to vdda with r = 50 k ? and decouple with c=100nf to gnda. 14 y_start input digital input (active high). start frame read out. 15 y_clock input digital input (active high). line clock. 16 last_line output digital output. generates a high level when the last line is read out. 17 x_load input digital input (active high). loads new x-position during read out. 18 sys_clock input digital input. system (pixel) clock (40 mhz). 19 pxl_valid output digital output. generates high level during pixel read out. 20 ss_start input digital input (active high). start synchronous shutter operation. 21 ss_stop input digital input (active high). stop synchronous shutter operation. 22 time_out output digital output. synchronous shutter: pulse when time-out reached. can be used to trigger ss_stop although both signals can?t be tied together. rolling shutter: pulse when second y-sync appears. 23 sys_reset input digital input (active high). global system reset. 24 el_black input digital input (active high). enables electrical black in output amplifier. 25 eosx output digital output. diagnostic end-of-scan of x-register.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 52 of 67 pin pin name pin type pin description 26 dac_vhigh input analog reference input. biasing of dac for output dark level. can be used to set output range of dac. default: connect to vdda with r = 0 ? . 27 dac_vlow input analog reference input. biasing of dac for output dark level. can be used to set output range of dac. default: connect to gnd a with r = 0 ? . 28 pxl_out1 output analog output. analog pixel output 1. 29 pxl_out2 output analog output. analog pixel output 2. leave not connected if not used. 30 amp_cmd input analog input. biasing of the output amplifier. connect to vdda with r = 50 k ? and decouple with c=100nf to gnda. 31 col_cmd input analog input. biasing of the column amplifiers. connect to vdda with r = 50 k ? and decouple with c=100nf to gnda. 32 pc_cmd input analog input. pre-charge bias. connect to vdda with r = 25 k ? and decouple with c=100nf to gnda. 33 vddd supply digital supply. digital supply voltage of the image sensor [3.3v]. 34 gndd ground digital ground. digital ground of the image sensor. 35 gnda ground analog ground. analog ground of the image sensor. 36 vdda supply analog supply voltage. analog supply voltage of the image sensor [3.3v]. 37 vddc supply analog supply voltage. supply voltage of the pixel core [3.3v]. 38 p_data<0> input digital input. data parallel interface (lsb). 39 p_data<1> input digital input. data parallel interface. 40 p_data<2> input digital input. data parallel interface. 41 p_data<3> input digital input. data parallel interface. 42 p_data<4> input digital input. data parallel interface. 43 p_data<5> input digital input. data parallel interface. 44 p_data<6> input digital input. data parallel interface. 45 p_data<7> input digital input. data parallel interface. 46 si2_addr<0> input 47 si2_addr<1> input 48 si2_addr<2> input 49 si2_addr<3> input 50 si2_addr<4> input unused interface inputs. tie to gndd. 51 gndab supply analog supply voltage. anti-blooming ground. 52 vddr_right supply analog supply voltage. variable reset voltage (multiple slope operation). decouple with 1uf to gnda. 53 adc_vlow input analog reference input. adc low reference voltage. default: connect to gnda with r = 360 ? and decouple with c=100nf to gnda. 54 adc_gnda ground analog ground. adc analog ground. 55 adc_vdda supply analog supply voltage. adc analog supply voltage [3.3v]. 56 adc_gndd ground digital ground. adc digital ground. 57 adc_vddd supply digital supply voltage. adc digital supply voltage [3.3v].
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 53 of 67 pin pin name pin type pin description 58 adc_clock input digital input. adc clock (40 mhz). 59 adc_out<9> output digital output. adc data output (msb). 60 adc_out<8> output digital output. adc data output. 61 adc_out<7> output digital output. adc data output. 62 adc_out<6> output digital output. adc data output. 63 adc_out<5> output digital output. adc data output. 64 adc_out<4> output digital output. adc data output. 65 adc_out<3> output digital output. adc data output. 66 adc_out<2> output digital output. adc data output. 67 adc_out<1> output digital output. adc data output. 68 adc_out<0> output digital output. adc data output (lsb). 69 adc_in input analog input. adc analog input. 70 adc_cmd input analog input. biasing of the input stage of the adc. connect to adc_vdda with r = 50 k ? and decouple with c=100nf to adc_gnda. 71 adc_vddd supply digital supply voltage. adc digital supply voltage [3.3v]. 72 adc_gnda ground analog ground. adc analog ground. 73 adc_gndd ground digital ground. adc digital ground. 74 adc_vdda supply analog supply voltage. adc analog supply voltage [3.3v]. 75 adc_vhigh input analog reference input. adc high reference voltage. default: connect to vdda with r = 90 ? and decouple with c=100nf to gnda. 76 vddr_left supply analog supply voltage. high reset level [4.5v]. 77 vddh supply analog supply voltage. high supply voltage for hold switches in the image core [4.5v] 78 p_data<15> input digital input. data parallel interface (msb). 79 p_data<14> input digital input. data parallel interface. 80 p_data<13> input digital input. data parallel interface. 81 p_data<12> input digital input. data parallel interface. 82 p_data<11> input digital input. data parallel interface. 83 p_data<10> input digital input. data parallel interface. 84 p_data<9> input digital input. data parallel interface. remarks : 1. all pins with the same name can be connected together. 2. all digital input are active hi gh (unless mentioned otherwise). 3. digital inputs that are not used should be tied to gnd.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 54 of 67 6 pad position and packaging 6.1 bare die the ibis5-a-1300 image sensor has 84 pins, 21 pins on every edge. the die size from pad-edge to pad-edge (without scribe-line) is: 10048.55 m (x) by 9240.30 m (y) scribe lines will take about 100 to 150 m extra on each side. pin 1 is located in the middle of the left side, indicated by a ?1? on the layout. a logo and some identification tags can be found on the top right of the die. p ad 1 identification pad 11 p ad 12 pad 32 pad 75 p ad 33 p ad 53 p ad 74 pad 54 8576.0 m (1280 * 6.7) 5028.6 m 6860.8 m (1024 * 6.7) 5039.5 m 10048.6 m 9240.3 m p ixel array cente r p ixe l 0,0 test structure origin ( 0,0 ) 771.6 m 1607.9 m 732.4 m 740,2 m figure 29: ibis5-a-1300 bare die dimensions
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 55 of 67 6.2 ibis5-a-1300 in 84-pins lcc package 6.2.1 technical drawing of the 84-pins lcc package figure 30: top view of the 84-pins lcc package (all dimensions in mm). figure 31: side view of the 84-pins lcc package (all dimensions in mm).
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 56 of 67 table 30: side view dimensions. (inch) (mm) dimensio n description min typ max min typ max a glass (thickness) ? mono 0.020 0.022 0.024 0.500 0.550 0.600 b cavity (depth) 0.060 0.069 0.078 1.520 1.750 1.980 c die ? si (thickness) ? mono 0.029 0.740 d bottom layer (thickness) 0.020 0.500 e die attach-bondline (thickness) 0.001 0.002 0.004 0.030 0.060 0.090 f glass attach-bondline (thickness) 0.001 0.003 0.004 0.030 0.070 0.110 g imager to lid-outer surface 0.062 1.570 h imager to lid-inner surface 0.037 0.950 j imager to seating plane of package 0.050 0.051 0.052 1.270 1.300 1.330 figure 32: side view dimensions. p in 1 figure 33: bottom view of the 84-pins lcc package (all dimensions in mm).
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 57 of 67 6.2.2 bonding of the ibis5-a-1300 se nsor in the 84-pins lcc package figure 34: bonding of the ibis5-a-1300 in the 84-pins lcc package. pixel 640,512
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 58 of 67 6.2.3 die placement of the ibis5-a-1300 in the 84-pins lcc package figure 35: die placement of the ibis5-a-1300 in th e 84-pins lcc package (all dimensions in mm). tolerance on the die placement in x- and y-directions is maximal +/- 50 um. 15,24 7,62 7,62 10,049 15,24 7,42 7,82 9,24 pixel 640,512
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 59 of 67 6.3 cover glass 6.3.1 monochrome sensor a d263 glass lid (which has a refraction index of 1.52) will be used as protection glass lid on top of the ibis5-a-1300 monochrome sens ors. figure 36 shows the transmission characteristics of the d263 glass. 0 10 20 30 40 50 60 70 80 90 100 400 500 600 700 800 900 wavelength [nm] transmission [%] figure 36: transmission characteristics of the d263 glass used as protective cover for the ibis5-a-1300 sensors.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 60 of 67 6.3.2 color sensor a s8612 glass lid (which has a refraction index of 1.55) will be used as nir cut-off filter on top of the ibis5-a-1300-c color image se nsor. figure 37 shows the transmission characteristics of the s8612 glass. figure 37: transmission characteristics of the s8612 glass used as protective cover for the ibis5-a-1300 sensors
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 61 of 67 figure 38: color response of the ibis5-a-1300-c in combination with the s8612 nir filter
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 62 of 67 7 storage and handling 7.1 storage conditions table 31: storage conditions. description minimum maximum units conditions temperature -10 66 c @ 15% rh temperature -10 38 c @ 86% rh note: rh = relative humidity 7.2 handling and solder precautions special care should be given when soldering im age sensors with color filter arrays (rgb color filters), onto a circuit board, since colo r filters are sensitive to high temperatures. prolonged heating at elevated temperatures may result in deterioration of the performance of the sensor. the following recommendati ons are made to ensure that sensor performance is not compromised duri ng end-user?s assembly processes. board assembly: device placement onto boards should be done in accordance with stri ct esd controls for class 0, jesd22 human body model, and cl ass a, jesd22 machine model devices. assembly operators should always wear all designated and approved grounding equipment; grounded wrist straps at es d protected workstations are recommended including the use of ionized blowers. all tools should be esd protected. manual soldering: when a soldering iron is used the fo llowing conditions s hould be observed: use a soldering iron with temperature control at the tip. the soldering iron tip temperature should not exceed 350 c. the soldering period for each pin should be less than 5 seconds. reflow soldering: figure 39 shows the maximum recommended thermal profile for a reflow soldering system. if the temperature/time profile exceeds these recommendations damage to the image sensor may occur.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 63 of 67 figure 39: reflow soldering temperature / time profile precautions and cleaning: avoid spilling solder flux on the cover glass; bare glass and par ticularly glass with antireflection filters may be adversely a ffected by the flux. avoid mechanical or particulate damage to the cover glass. it is recommended that isopropy l alcohol (ipa) is used as a solvent for cleaning the image sensor glass lid. when using other solvents , it should be confir med beforehand whether the solvent will dissolve the pack age and/or the glass lid or not.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 64 of 67 8 ordering information table 32: fillfactory and cypress part numbers fillfactory part number cypress semiconductor part number ibis5-a-1300-m-1 cyii5sm1300aa-hbc (preliminary) ibis5-a-1300-m-2 cyii5sm1300aa-qbc (preliminary) ibis5-a-1300-c-1 cyii5sc1300aa-hac (preliminary) ibis5-a-1300-c-2 cyii5sc1300aa-qac (preliminary) disclaimer fillfactory image sensors are only warranted to meet the specifications as described in the production data sheet. fillfactory reserv es the right to change any information contained herein without notice. please contact info@fillfactory.com for more information. revision changes no. date description of revision 1.0 22-jun-04 origination. 1.1 16-sep-04 3.10.2.g. additional explan ation about the test pattern use. 5 pin list. recommended values of pins 30, 31, 76 and 77 corrected. 6.3 refraction index of both colo r and mono glass lid added. 1.2 24-sep-04 3.8.4 table 17. adc reference voltages updated. 1.3 04-jan-2005 added cypres s equivalent part numbe rs, part ordering table added cypress document # 38-05710 rev ** in the document footer.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 65 of 67 appendix a: ibis5 evaluation system for evaluating purposes an ibis5 ev aluation kit is available. the ibis5 evaluation kit consis ts of a multifunctional digita l board (memory, sequencer and ieee 1394 fire wire interface) a nd an analog image sensor board. visual basic software (under win 2000 or xp) allows the grabbing and display of images and movies from the sensor. all acquired imag es and movies can be stored in different file formats (8 or 16-bit). all setting can be adjusted on the fly to evaluate the sensors specs. default register values can be loaded to start the software in a desired state. figure 40: content of the ibis5 evaluation kit please contact fillfactory ( info@fillfactory.com ) for more information on the evaluation kit.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 66 of 67 appendix b: frequently asked questions q: how does the dual (multiple) slope extended dynamic range mode works? a: dual slope is a method to extend the dynamic range of a normally linear-transfer imager, by combining the images taken with a long integration time (dark areas of a scene) and a short integration time (bright areas of a scene) into one image. the resulting electro-optical transfer curve is bi-linear. multiple slope is an extension of it, resulting in a multi-linear transfer curve with multiple knee points. figure 41: double slope response please look at our website to find some pictures taken with the ibis4-1300 in double slope mode on: http://www.fillfactory.be/ht m/technology/htm/dual-slope.htm . please contact support@fillfactory.com for additional application notes to use the multiple slope extended dynamic rang e mode with the ibis5-a-1300 sensor.
ibis5-a-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #: 38-05710 rev.**(revision 1.3) page 67 of 67 document history page document title: IBIS5A-1300 1.3m pixel dualshutter mode cmos image sensor document number: 38-05710 rev. ecn no. issue date orig. of change description of change ** 310213 see ecn sil initial cypress release (eod)

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